1. Field of the Invention
The present invention relates to a clock buffer circuit and a clock signal buffering method which amplify a clock signal sent to a semiconductor integrated circuit. More particularly, the present invention relates to a clock buffer circuit and a clock signal buffering method which can suppress current consumption.
2. Description of the Related Art
Conventionally, an amplitude of a clock signal sent to a semiconductor integrated circuit is different depending on a supply source of the clock signal. Thus, the clock signal may have an amplitude that is sufficiently large for the operation of the semiconductor integrated circuit or have an amplitude which is not sufficiently large enough for the operation of the semiconductor integrated circuit.
Therefore, a clock buffer circuit is used to amplify the clock signal which is not sufficiently large for the operation of the semiconductor integrated circuit. In the clock buffer circuit, when the clock signal is inputted which is not sufficiently large for the operation of the semiconductor integrated circuit, the clock signal is amplified to the sufficiently high level for the operation of the semiconductor integrated circuit, and the amplified clock signal is inputted to the semiconductor integrated circuit.
However, in a conventional clock buffer circuit, a feedback loop is executed. In this case, even if a clock signal is inputted whose amplitude is large enough that it doesn't need to be amplified, a current corresponding to the clock signal flows through the feedback loop. This results in the useless consumption of electrical power by the current.
Japanese Laid Open Patent Application (JP-A-Heisei 8-130462) discloses a clock buffer circuit as described below. That is, the clock buffer circuit includes a first buffer circuit, a second buffer circuit, a switching circuit and a switch control circuit. The first buffer circuit performs a buffer operation to a first clock signal. The second buffer circuit performs a buffer operation to a second clock signal which is an inverse signal to the first clock signal. The switching circuit is connected between a first clock signal output line connected with an output end of the first buffer circuit, and a second clock signal output line connected with an output end of the second buffer circuit. The switch control circuit operates such that the switching circuit is conducting for a predetermined period when the first and second clock signals are inverted relative to each other, and the switching circuit is not conducting for a period other than the predetermined period.
In the clock buffer circuit, when the first clock signal is inverted from L to H, a part of charges accumulated in parasitic capacitance of the first clock signal output line is transferred through the switching circuit to the side of the second clock signal output line. On the other hand, when the second clock signal is inverted from L to H, a part of charges accumulated in parasitic capacitance of the second clock signal output line is transferred through the switching circuit to the side of the first clock signal output line. As mentioned above, the part of the charges transferred from the parasitic capacitance of the first (second) clock signal output line is used effectively, when the second (first) clock signal is inverted. Correspondingly, the charges (current) to be supplied to the second (first) clock signal output line can be suppressed, when the second (first) clock signal is inverted.
However, the clock buffer circuit disclosed in the above-mentioned prior art cannot suppress the useless consumption of the current, when the clock signal whose amplitude is large enough to operate the semiconductor integrated circuit is inputted to the clock buffer circuit.